Minimization power and non-linearity errors with split SAR ADC

This paper introduces the linearity analysis of a progressive successive approximation registers (SAR) simple toadvanced converters (ADC) with part DAC structure taking into account two exchanging techniques: conventional charge-redistribution and Vcm-based switching. The static linearity execution, in particular the fundamental nonlinearity and differential nonlinearity, and in addition the parasitic impacts of the part DAC, are dissected hereunder. What's more, a code-randomized adjustment strategy is proposed to minimize the the transformation nonlinearity in the ordinary SAR ADC, which is confirmed by behavioral simulation, and measured results. Exhibitions of both exchanging conventional are shown in 90 nm CMOS. Estimation consequences of power, speed, and linearity plainly demonstrate the profits of utilizing Vcm-based exchanging.